As semiconductor process dimensions continue to shrink, integrated circuit (IC) designs scale up increasingly. Requirements imposed on highly complex ICs become more and more stringent, such as higher reliability, higher quality, lower cost and shorter time-to-market cycles. On the one hand, the shrinking semiconductor process dimensions lead to more types of possible deficiencies of embedded memory devices. On the other hand, with the complexity of IC products increasing, the proportion of ROMs, RAMs, and EEPROMs therein continues to rise.
Design-for-Testability (DFT) techniques for embedded memory devices include direct testing, embedded CPU-based testing and Memory Built-in Self-Test (MBIST). MBIST is advantageous over the other two schemes in many aspects. Firstly, MBIST allows automatic DFT and automatic realization of test algorithms for general memory devices, and can thus achieve high test quality and low test cost. Secondly, MBIST circuits are capable of “full speed” testing based on the system clock and can thus cover more generated defects and reduce testing time. Thirdly, MBIST imparts self-diagnosis and self-repairing capacities to most memory devices. In addition, MBIST initialization test vectors can be run on very low cost test equipment. Therefore, MBIST is currently a mainstream DFT technique for embedded memory devices in view of high test quality and low test cost.
FIG. 1 is a schematic diagram of a first MBIST circuit of the prior art. As shown in FIG. 1, at the beginning of a testing process, a test instrument (not shown) delivers a reset signal to a test chip or wafer via a pin RESETb to restore the control logic circuit to its primary default state and powers the test chip or wafer via another pin VPP TMO. During the testing process, the test instrument transmits input data TDI at a clock frequency TCK. After being decoded by a MBIST control circuit, the input data TDI are activated by a trigger signal STROBE from the test instrument and then cooperate with the control logic circuit to test the circuit of the memory device such as a flash memory device. With the testing being completed, the test data or results are returned to the test instrument as test output data TDO under the control of the control logic circuit. The test instrument then compares the input TDI and output TDO and thereby verifies whether the circuit of the memory device such as a flash memory device meets or satisfies the predefined performance criteria.
For the MBIST circuit, the number of its control pins directly determines how many chip dies the MBIST circuit can test at the same time. As described above, the MBIST circuit of the prior art requires six pins, i.e., those for the test input data TDI, test output data TDO, test trigger signal STROBE, test clock TCK, test power supply VPP_TM0 and reset signal RESETb, indicated by the crossed boxes in FIG. 1. Given the fact that a typical probe card has 768 signal testing probes, and since the MBIST circuit of the prior art requires 6 pins, the number of simultaneously testable chip dies is 768/6=128, which is not efficient.
Referring now to FIG. 2, which is a schematic diagram of a second MBIST circuit of the prior art, in order to reduce the number of used pins, the second MBIST circuit replaces the pins TDI and TDO for the test input and out data with a single data interface pin IO, and internally generates the test trigger signal and reset signal. As a result, three pins are saved, and the MBIST circuit requires only three pins, indicated by the crossed boxes in FIG. 2. This leads to an improvement in test efficiency.
However, even though the second MBIST circuit has achieved the saving of three pins, the number of chips dies that it can test at the same time is only 768/3=256. In order to further enhance the test efficiency, there is still a need for a MBIST circuit that requires the use of fewer pins.